As is well known, the number of transistors on integrated circuits approximately doubles every two years, in accordance with Moore's Law. However, the continuation of the classical metal-oxide-semiconductor field-effect-transistor (MOSFET) scaling beyond the 12 nm technology node will only be possible if device engineers replace the traditional silicon channel of e.g. a transistor by more powerful semiconductor materials. High carrier mobility materials such as germanium and/or compound semiconductor materials have now matured to an industrial development level, but even these materials reach their limits in view of very small devices. One of the fundamental limitations of MOSFETs is its subthreshold slope or more often used in its inverse term as subthreshold swing (SS), which describes the exponential behavior of the current in function of the voltage applied. The subthreshold swing is limited to 60 mV/decade (at room temperature being 300K) irrespective of the materials and geometries used. However for low power applications a faster switching is desired between off-state (off current) and on-state (on-current). Therefore SS should be decreased below 60 mV/dec.
An alternative device concept explored nowadays which has a decreased SS below 60 mV/decade is the tunneling field-effect-transistor (TFET). A TFET device comprises a p-i-n structure and its working mechanism is based on gate-controlled band-to-band tunneling. p-type TFET devices are however difficult to manufacture. TFET devices make use of doped source and drain regions wherein the quality of the interface between the different doping regions (being chemically doped or by using a heterostructure) may influence the tunneling mechanism. Especially in group IV and group III-V based TFET devices the interface quality becomes important as interface defects may induce trap-assisted tunneling or interband tunneling in the off state (device is turned off) and as a consequence will influence the lon/loff properties of the TFET device.
Another possible device concept which has sub-60 mV/decade SS is an energy-filtered FET. U.S. Pat. No. 8,129,763 B2 discloses an energy-filtered FET comprising a channel in between a source and drain, a gate proximate the channel configured to control the conduction of the channel and between the source and channel an energy filter to control the injection of carriers. The energy filter includes a superlattice structure. The superlattice structure is realized as a multilayer periodic structure of alternating semiconductor layers with wide and narrow band gaps thereby forming so called mini-bands. Superlattice structures may be formed using epitaxial techniques or sputtering. The formation and integration of a superlattice in a FET is however not easy. Moreover as a periodic structure of layers of two or more materials is formed, the interface defects between the different layers also need to be controlled. III-V materials tend to intermix such that it is difficult to build a sharp interface between the different materials of the superlattice. Also the number of periods needed is high, as such making the device hard to scale to smaller dimensions.
There is a need for new device concepts with sub-60 mV/decade SS which may be easily manufactured.